Title :
Deep sub-100 nm Ge CMOS devices on Si with the recessed S/D and channel
Author :
Heng Wu ; Wei Luo ; Mengwei Si ; Jingyun Zhang ; Hong Zhou ; Ye, Peide D.
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Abstract :
We report on comprehensive studies of Ge CMOS devices with the recessed channel and S/D fabricated on a Ge-on-insulator (GeOI) substrate. Both nFETs and pFETs with channel lengths (Lch) from 500 to 20 nm, channel thicknesses (Tch) from 90 to 15 nm, EOTs from 5 to 3 nm, and gate stacks with and without the post oxidation (PO) are investigated. Benefiting from the fully depleted ultra-thin body (FD-UTB) channel with a reasonable interface, a low sub-threshold slope (SS) of 95 mV/dec is obtained in a 60 nm Lch nFET and a record high ION/IOFF ratio of 106 is realized in a 300 nm Lch nFET. The recessed contact strongly dependents on the recessed depth and optimized recessed depth significantly improves the Ge contacts.
Keywords :
CMOS integrated circuits; Ge-Si alloys; low-power electronics; optimisation; GeSi; deep CMOS devices; fully depleted ultra-thin body channel; gate stacks; nFET; pFET; post oxidation; recessed channel; recessed contact; recessed depth; size 300 nm; size 5 nm to 3 nm; size 500 nm to 20 nm; size 60 nm; size 90 nm to 15 nm; Aluminum oxide; Etching; Iterative closest point algorithm; Logic gates; Measurement; Oxidation; Silicon;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7047067
