Architecture for an aVLSI stereo vision system

Author

Philipp, RalfM ; Reddy, Viswabharath ; Etienne-Cummings, Ralph ; Lewis, M. Anthony

Author_Institution

Dept. of Electr. & Comput. Eng., Johns Hopkins Univ., Baltimore, MD, USA

Volume

3

fYear

2002

fDate

6/24/1905 12:00:00 AM

Firstpage

691

Lastpage

694

Abstract

This paper introduces a depth-computation architecture designed for, but not limited to, a single-chip current mode analog VLSI (aVLSI) implementation of stereo vision. The architecture implements a modified version of the block matching algorithm; pixel blocks are averaged (summed) vertically before comparison along the horizontal axis. This both reduces the effects of noise and provides an order-of-magnitude reduction in computational complexity. Simulation results indicate performance on par with a full implementation of block matching

Keywords

VLSI; analogue integrated circuits; computational complexity; computer architecture; computer vision; current-mode circuits; digital simulation; stereo image processing; block matching algorithm; computational complexity; confidence tests; depth-computation architecture; horizontal disparity; noise; pixel blocks; single-chip current mode analog VLSI; stereo vision; Algorithm design and analysis; Cameras; Computational complexity; Computer architecture; Mirrors; Noise reduction; Pixel; Robots; Stereo vision; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010318

Filename

1010318