DocumentCode :
3565185
Title :
InGaAs/InAs heterojunction vertical nanowire tunnel fets fabricated by a top-down approach
Author :
Xin Zhao ; Vardi, Alon ; del Alamo, Jesus A.
Author_Institution :
Microsyst. Technol. Labs., Massachusetts Inst. of Technol., Cambridge, MA, USA
fYear :
2014
Abstract :
We demonstrate for the first time InGaAs/InAs heterojunction single nanowire (NW) vertical tunnel FETs fabricated by a top-down approach. Using a novel III-V dry etch process and gate-source isolation method, we have fabricated 50 nm diameter NW TFETs with a channel length of 60 nm and EOT=1.2 nm. Thanks to the insertion of an InAs notch, high source doping, high-aspect ratio nanowire geometry and scaled gate oxide, an average subthreshold swing (S) of 79 mV/dec at Vds= 0.3 V is obtained over 2 decades of current. On the same device, Ion= 0.27 μA/μm is extracted at Vdd= 0.3 V with a fixed Ioff= 100 pA/μm. This is the highest ON current demonstrated at this OFF current level in NW TFETs containing III-V materials.
Keywords :
III-V semiconductors; etching; field effect transistors; gallium arsenide; indium compounds; nanofabrication; nanowires; semiconductor heterojunctions; tunnel transistors; III-V dry etch process; InGaAs-InAs; NW TFET; NW vertical tunnel FET; gate-source isolation method; heterojunction single nanowire; heterojunction vertical nanowire tunnel FET; subthreshold swing; top-down approach; voltage 0.3 V; Heterojunctions; Indium gallium arsenide; Logic gates; Metals; Silicon; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
Type :
conf
DOI :
10.1109/IEDM.2014.7047108
Filename :
7047108
Link To Document :
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