Title :
Highly dependable 3-D stacked multicore processor system module fabricated using reconfigured multichip-on-wafer 3-D integration technology
Author :
Lee, K.-W. ; Hashimoto, H. ; Onishi, M. ; Konno, S. ; Sato, Y. ; Nagai, C. ; Bea, J.-C. ; Murugesan, M. ; Fukushima, T. ; Tanaka, T. ; Koyanagi, M.
Author_Institution :
New Ind. Creation Hatchery Center (NICHe), Tohoku Univ., Sendai, Japan
Abstract :
A highly dependable 3-D stacked multicore processor module composed of 4-layer stacked 3-D multicore processor chip and 2-layer stacked 3-D cache memory chip is implemented using reconfigured multichip-on-wafer 3-D integration and backside TSV technologies for the first time. Tier boundary scan, self-repair circuits, and BIST circuits in the 4-layer stacked 3-D multicore processor chip and the basic read/write functions of memory circuits in the 2-layer stacked 3-D cache memory chip are successfully evaluated. High-density TSVs and micro-joining characteristics in the 3-D stacked chip were evaluated by a non-destructive method using high resolution X-ray CT scanning tool.
Keywords :
boundary scan testing; built-in self test; cache storage; integrated circuit testing; maintenance engineering; multichip modules; multiprocessing systems; three-dimensional integrated circuits; 2-layer stacked 3D cache memory chip; 4-layer stacked 3D multicore processor chip; BIST circuit; backside TSV technology; basic read-write memory circuit; high resolution X-ray CT scanning tool; highly dependable 3D stacked multicore processor system; microjoining characteristics; module; nondestructive method; reconfigured multichip-on-wafer 3D integration technology; self-repair circuit; tier boundary scan; Built-in self-test; Cache memory; Image sensors; Multicore processing; Reliability; Semiconductor device measurement; Through-silicon vias;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7047128
