Title :
A new high-k/metal gate CMOS integration scheme (Diffusion and Gate Replacement) suppressing gate height asymmetry and compatible with high-thermal budget memory technologies
Author :
Ritzenthaler, R. ; Schram, T. ; Spessot, A. ; Caillat, C. ; Cho, M. ; Simoen, E. ; Aoulaiche, M. ; Albert, J. ; Chew, S.A. ; Noh, K.B. ; Son, Y. ; Fazan, P. ; Horiguchi, N. ; Thean, A.
Author_Institution :
imec, Leuven, Belgium
Abstract :
A new scheme called in the following “Diffusion and Gate Replacement” (D&GR) MIPS integration is demonstrated. The CMOS flow allows to control the gate height asymmetry between NMOS and PMOS by driving the work function shifter directly into the high-k. Since the threshold voltage (Vth) shifter sources are removed, it is compatible with other processes requiring high-thermal budget such as memory technologies (DRAM periphery).
Keywords :
CMOS digital integrated circuits; DRAM chips; high-k dielectric thin films; D&GR MIPS integration; DRAM periphery; NMOS; PMOS; diffusion and gate replacement; gate height asymmetry suppression; high-k-metal gate CMOS integration scheme; high-thermal budget memory technologies; work function shifter; Aluminum oxide; Annealing; High K dielectric materials; Logic gates; MOS devices; Tin;
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
DOI :
10.1109/IEDM.2014.7047154
