Hybrid Si/TMD 2D electronic double channels fabricated using solid CVD few-layer-MoS2 stacking for Vth matching and CMOS-compatible 3DFETs

Author

Min-Cheng Chen ; Chia-Yi Lin ; Kai-Hsin Li ; Lain-Jong Li ; Chang-Hsiao Chen ; Cheng-Hao Chuang ; Ming-Dao Lee ; Yi-Ju Chen ; Yun-Fang Hou ; Chang-Hsien Lin ; Chun-Chi Chen ; Bo-Wei Wu ; Cheng-San Wu ; Yang, Ivy ; Yao-Jen Lee ; Wen-Kuan Yeh ; Tahui Wang ;

Author_Institution

Nat. Nano Device Labs., Nat. Appl. Res. Labs., Taipei, Taiwan

fYear

2014

Abstract

Stackable 3DFETs such as FinFET using hybrid Si/MoS₂ channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS₂ to Si fin and nanowire resulted in improved (+25%) I_on,n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V_th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.

Keywords

CMOS integrated circuits; MOSFET; chemical vapour deposition; elemental semiconductors; molybdenum compounds; nanowires; silicon; stacking; CMOS-compatible 3DFET; FinFET; N-P device; PFET; Si-MoS₂; V_th matching; hybrid Si-TMD 2D electronic double channels; molecular layers; nanowire FET; silicon fin; silicon nanowire; solid CVD few-layer-stacking; stackable 3DFET; transition metal dichalcogenide; FinFETs; Logic gates; Performance evaluation; Silicon; Substrates; Three-dimensional displays; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2014 IEEE International

Type

conf

DOI

10.1109/IEDM.2014.7047163

Filename

7047163