DocumentCode :
3565282
Title :
Accurate prediction of PBTI lifetime for N-type fin-channel tunnel FETs
Author :
Mizubayashi, W. ; Mori, T. ; Fukuda, K. ; Liu, Y.X. ; Matsukawa, T. ; Ishikawa, Y. ; Endo, K. ; O´uchi, S. ; Tsukada, J. ; Yamauchi, H. ; Morita, Y. ; Migita, S. ; Ota, H. ; Masahara, M.
Author_Institution :
Nanoelectron. Res. Inst. (NeRI), Nat. Inst. of Adv. Ind. Sci. & Technol. (AIST), Tsukuba, Japan
fYear :
2014
Abstract :
The positive bias temperature instability (PBTI) characteristics for n-type fin-channel tunnel FETs (TFETs) with high-k gate stacks have been thoroughly investigated and compared with conventional FinFETs. The subthreshold slope (SS) is not degraded at all while the threshold voltage (Vth) shifts in the positive direction by the PBTI stress. The activation energy of ΔVth for TFETs is almost the same as FinFETs, indicating that the PBTI mechanism for TFETs is almost the same as FinFETs. It was found that, by applying a positive bias to the n+-drain (normal operation condition), the PBTI lifetime is dramatically improved as compared with that in the conventional stress test (both the p+-source and n+-drain are grounded). This is because carrier injection from the n+-drain is the main cause of the PBTI, especially for n-type TFETs. Thus, the realistic impact of the PBTI is significantly mitigated for n-type TFETs.
Keywords :
field effect transistors; high-k dielectric thin films; tunnel transistors; PBTI lifetime; TFET; carrier injection; high-k gate stacks; n-type fin-channel tunnel FET; n+-drain; normal operation condition; positive bias temperature instability; Degradation; FinFETs; Logic gates; Stress; Temperature measurement; Tunneling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2014 IEEE International
Type :
conf
DOI :
10.1109/IEDM.2014.7047167
Filename :
7047167
Link To Document :
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