Author :
Souare, P.M. ; Coudrain, P. ; Colonna, J.P. ; Fiori, V. ; Farcy, A. ; de Crecy, F. ; Borbely, A. ; Ben-Jamaa, H. ; Laviron, C. ; Gallois-Garreignot, S. ; Giraud, B. ; Hotellier, N. ; Franiatte, R. ; Dumas, S. ; Chancel, C. ; Riviere, J.-M. ; Pruvost, J. ;
Abstract :
We present an advanced and comprehensive platform for thermal dissipation studies in TSV-based 3D ICs. A 2-tier 3D test chip with through silicon via (TSV) and μ-bump is used for thermal characterization with unprecedented precision and design exploration capabilities. A comprehensive calibrated 3D finite element model is associated to provide a predictive tool that is able to simulate the thermal mapping in any given 3D interconnect configuration with minimal error. Guidelines are finally provided for thermal optimization of 3D designs with a precision far beyond the prior art.
Keywords :
finite element analysis; integrated circuit interconnections; integrated circuit testing; thermal analysis; three-dimensional integrated circuits; μ-bump; 2-tier 3D test chip; 3D finite element model; 3D interconnect configuration; TSV-based 3D integrated circuit; thermal characterization; thermal dissipation study; thermal mapping; through silicon via; Heating; Integrated circuit interconnections; Numerical models; Solid modeling; Temperature measurement; Three-dimensional displays; Through-silicon vias; 3D ICs; FEM simalution; TSV; Thermal; self heating; sensor; thermoelectric measurement;
