A new surface potential-based compact model for a-IGZO TFTs in RFID applications

For the first time, we present a surface potential-based compact model for a-IGZO TFTs based on multiple trapping-release theory and benchmark our work against device measurements. This model does not require time-consuming calculation. Meanwhile, we have developed the automatic parameter extraction program, which can extract the parameters rapidly and accurately. Moreover, the compact model is coded in Verilog-A, and implemented in a vendor CAD environment. This model provides physics-based consistent description of DC and AC device characteristics and enables accurate circuit-level performance prediction and RFID circuit design of a-IGZO TFTs.