FPGA-based architecture of 3-D HWT using distributed arithmetic (DA)

This paper describes the design and implementation of three-dimensional (3-D) Haar with transpose-based computation and distributed arithmetic (DA). As a results of the separately property of the multi-dimensional Haar wavelet transform (HWT), the proposed architecture has been implemented using a cascade of three N-point one-dimensional (1-D) Haar and two transpose memories for a 3-D volume of N × N × N, suitable for 3-D medical image compression. The 3-D HWT architecture were implemented on SubRIO-9632 board National Instrument. Experimental result and analysis of area, power consumption and maximum frequency are discussed in this paper.