Static voltage drop and current density analysis for high performance FPGA flip-chip package design

As the FPGA device performance increases and integrated circuit reduces in size there will be more and more challenges on the package design. Detailed analysis to capture and address design challenges is important for a viable power distribution network (PDN) package design. This paper will discuss the modeling methodology to analyze the static voltage drop for the high performance and high density FPGA flip-chip packages. Thru the analysis, the design solution to optimize the IR drop and EM problem will be presented.