Quantitative reliability prediction model for wafer level packages under board-level temperature cycling

A damage accumulation based interconnect fatigue failure model is developed for predicting the board-level temperature cycling (T/C) reliability of wafer level packages (WLPs). Creep and constant strain rate experiments were first performed to characterize the viscoplastic constitutive behavior of Pb-free solder. Finite element (FE) analyses based on the viscoplastic models were conducted for estimating inelastic strain energy density accumulation. The numerical results were then compared to a library of board-level T/C reliability test results for best fitting the reliability model. Factors such as alloy Ag content, package geometry, and ball grid array (BGA) layout are considered in the model.