DocumentCode :
3565913
Title :
Channel noise scan by using simulations of voltage regulator noise to signals
Author :
Hsu, Jimmy ; Chang, Patt ; Su, Thonas ; Gong Ouyang ; Kai Xiao ; Lee, Falconee ; Li, Y.L.
Author_Institution :
DCG, Intel Microelectron. Asia Ltd., Taipei, Taiwan
fYear :
2014
Firstpage :
125
Lastpage :
128
Abstract :
In this paper, channel noise scan approach (CNS) is proposed to efficiently analyze the potential VR-signal coupling issue in the pre-silicon design and the post-silicon debug of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction between the two. The goal of this simulation methodology is to help platform developer to quantify the VR-signal coupling risk and find the outliers of the victim signal nets according to the board layout and the VR design. This methodology can also provide the ability for the designer to do performance/cost tradeoff, layout optimization. To systematically analyze the VR-signal coupling problems, both the frequency and time domain approaches have been developed to characterize the VR-signal coupling in different levels. The frequency domain approach can quickly point out potential issues and the time domain approach is proved to be consistent with the frequency domain but with more detail and intuitive information. A design flow is given to efficiently identify the outliers of victim signals by VR noise coupling impact. Designers can improve the layout based on channel noise scan results from the simulations.
Keywords :
electron device noise; frequency-domain analysis; time-domain analysis; voltage regulators; CNS; PCB; VR-signal coupling issue; channel noise scan approach; frequency domain approaches; layout optimization; performance-cost tradeoff; platform development; post-silicon debug; pre-silicon design; time domain approaches; victim signal nets; voltage regulator networks; Couplings; Frequency-domain analysis; Integrated circuit modeling; Layout; Noise; Switches; Voltage control;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2014 9th International
Type :
conf
DOI :
10.1109/IMPACT.2014.7048424
Filename :
7048424
Link To Document :
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