Research of electroplating and electroless plating for low temperature bonding in 3D heterogeneous integration

Author

Yu-Chen Hu ; Yao-Jen Chang ; Chun-Shen Wu ; Yung Mao Cheng ; Wei Jen Chen ; Kuan-Neng Chen

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2014

Firstpage

290

Lastpage

293

Abstract

In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270°C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn μ-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 μm bump pitch, 40 μm diameter of Cu/Sn μ-bump and 50 μm diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.

Keywords

bonding processes; copper; electroplating; three-dimensional integrated circuits; tin; 3D chip-to-chip hetero-integration scheme; 3D heterogeneous integration; Cu; Sn; advanced technology node logic chips; common technology node logic chips; electroless plating; electroplating; low temperature bonding; size 40 mum; size 50 mum; size 60 mum; Bonding; Gold; Integrated circuits; Joints; Scanning electron microscopy; Three-dimensional displays; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT), 2014 9th International

Type

conf

DOI

10.1109/IMPACT.2014.7048426

Filename

7048426