aS3-plus — Reinventing the QFN and wafer level fan out package

Smart phone & portable devices have dominated the Semiconductor growth, and drive the IC packages to smaller, lighter & thinner, but integrate more function. Besides SOC solution being driven by design house or system company, we have seen more packages of Quad Flat Non-lead (QFN), wafer level CSP (WLCSP), fan out WLCSP (FOWLP) and system in package (SIP) are being widely used in smart phone & mobile devices. To order to integrating more function and improve performance, the carrier (or substrate) for IC packages have to have finer pitch & rout-ability for more IO in the same body size. According to such a requirement, ASE have done and developed a new package solution, aS³-Plus, with fine pitch & routable (design flexibility) capability, which is able to adapt by both wire bonding and flip chip connection technology. It is also suitable for SiP heterogeneous integration including passives, sensors and MENS. aS³-Plus is designed to single layer metal trace and good rout-ability, which can keep the good thermal performance as QFN, but also improve the design flexibility and capability, which is helpful to shorten the wire length and lower resistance for RF product or resistance sensitive product, like power management IC (PMIC). aS³-Plus is also designed to trace embedded, and fine line width and space (15/15um trace line width/space now, and would be 12/12um and beyond by end of 2014). Multiple layers are being developed. With such a feature of fine pitch & trace rout-ability, aS³-Plus can combine cu pillar bump to offer a good performance by flip chip connection and chip scale package (CSP) solution. This would be a good alternative solution of fan-out WLCSP. Cu pillar bump & routable aS³-Plus substrate can offer the shortest signal path and less resistant performance. Comparing to fan-out WLCSP, silicon is connected by lead free soldering (Cu pillar solder cap) aS^3\n\n\t\t