Title :
Distributed sleep transistors network for power reduction
Author :
Long, Changbo ; He, Lei
Author_Institution :
ECE Dept., Univ. of Wisconsin, Madison, WI, USA
Abstract :
Sleep transistors are effective to reduce dynamic and leakage power. The cluster-based design was proposed to reduce the sleep transistor area by clustering gates to minimize the simultaneous switching current per cluster and then inserting a sleep transistor per cluster. In the paper, we propose a novel distributed sleep transistor network (DSTN), and show that DSTN is intrinsically better than the cluster-based design in terms of the sleep transistor area and circuit performance. We reveal properties of optimal DSTN designs, and then develop an efficient algorithm for gate level DSTN synthesis. The algorithm obtains DSTN designs with up to 70.7% sleep transistor area reduction compared to cluster-based designs. Furthermore, we present custom layout designs to verify the area reduction by DSTN.
Keywords :
CMOS integrated circuits; MOSFET; circuit optimisation; low-power electronics; power consumption; power control; semiconductor device models; CMOS gate; DSTN design algorithm; area reduction; cluster-based design; distributed sleep transistor; gate level synthesis; layout designs; minimize switching current; power reduction; sleep transistors network; Algorithm design and analysis; Clustering algorithms; Energy consumption; Integrated circuit synthesis; Network synthesis; Performance loss; Permission; Propagation delay; Sleep; Threshold voltage;
Conference_Titel :
Design Automation Conference, 2003. Proceedings
Print_ISBN :
1-58113-688-9
DOI :
10.1109/DAC.2003.1218937
