DocumentCode
3566772
Title
A study of a new flip chip packaging process for diversified bump and land combination
Author
Mizutani, Masaki ; Ito, Satoshi ; Kuwamura, Makoto ; Noro, Hiroshi ; Akizuki, Shin ; Prarhu, Ashok
Author_Institution
Nitto Denko Corp., Mie, Japan
fYear
1998
Firstpage
316
Lastpage
319
Abstract
Flip chip packages using plastic substrates are becoming popular in the IC packaging market. However, it still has not been standardized as a real mass production system. We have newly developed a flip chip packaging technology using a nonconductive underfill resin sheet. The process flow of the new flip chip packaging is as follows. First, the underfill sheet is laminated onto substrate. Next, the bumped die is aligned and attached onto substrate which is covered by the underfill sheet under proper heat and pressure. The bumps under the die penetrate the resin and to reach the metal land of the substrate. Finally curing the underfill sheet and metal connection are carried out. We have studied the possibility of applying this packaging technology to a diversified bump and land combination by changing the underfill component and process parameters. The electrical stability and package warpage under several stress test conditions, such as JEDEC Level-3 and TST, have been evaluated in this study. After this evaluation, we found that the packages which have been built with proper resin components and process parameters show good performance for all of these reliability tests almost regardless of bump and land materials
Keywords
flip-chip devices; integrated circuit packaging; integrated circuit reliability; soldering; IC packaging; JEDEC Level-3; TST; bumped die alignment; curing; die attach; diversified bump/land combination; electrical stability; flip chip packaging process; lamination; nonconductive underfill resin sheet; package warpage; plastic substrates; reliability tests; stress test conditions; Curing; Flip chip; Integrated circuit packaging; Mass production; Materials reliability; Plastic integrated circuit packaging; Resins; Stability; Stress; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components & Technology Conference, 1998. 48th IEEE
ISSN
0569-5503
Print_ISBN
0-7803-4526-6
Type
conf
DOI
10.1109/ECTC.1998.678712
Filename
678712
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