DocumentCode :
35671
Title :
Adapting an Implicit Path Delay Grading Method for Parallel Architectures
Author :
Lenox, Joseph ; Tragoudas, Spyros
Author_Institution :
Dept. of Electr. & Comput. Eng., Southern Illinois Univ. at Carbondale, Carbondale, IL, USA
Volume :
33
Issue :
12
fYear :
2014
fDate :
Dec. 2014
Firstpage :
1965
Lastpage :
1976
Abstract :
For large modern circuits, it is desirable to trade hardware cost for time when making path delay fault (PDF) coverage estimates, especially as a subroutine for automatic test pattern generation and timing analysis solutions. A parallel adaptation of an established framework for implicit PDF grading on with a general-purpose computing on graphics processing units (GPU) implementation is presented. Experimental evaluation on a NVIDIA Tesla C2075 GPU shows on average 50× speedup against the basic version for the framework on an Intel Xeon E5504 host system. Over a 1200× speedup is observed against a single-threaded, more complex version in the framework which grades more faults.
Keywords :
automatic test pattern generation; delays; graphics processing units; parallel architectures; GPU implementation; Intel Xeon E5504 host system; NVIDIA Tesla C2075 GPU; PDF coverage estimates; automatic test pattern generation; general-purpose computing; graphics processing units; implicit PDF grading; implicit path delay grading method; large modern circuits; parallel architectures; path delay fault coverage estimates; timing analysis solutions; Algorithm design and analysis; Benchmark testing; Circuit faults; Estimation; Graphics processing units; Parallel architectures; Delay testing; general-purpose computing on graphics processing units (GPGPU); logic simulation; timing verification;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2014.2356438
Filename :
6951872
Link To Document :
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