DocumentCode :
3567372
Title :
Power characterization of functional units
Author :
Ye, Wu ; Li, Kanning ; Cheng, Ming ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Volume :
1
fYear :
1999
Firstpage :
775
Abstract :
In cycle-accurate RTL level power estimation, a table is used to characterize the power consumed by each functional unit. The size of the table grows exponentially with the size of the inputs. We present a partitioning power modeling technique to reduce the table size. Results indicate that this technique works for shifters and register files with reasonable accuracy and much smaller table size. Results also show that by multiplying a constant factor, this technique also works for multipliers. Simulation time is reduced significantly. Similar techniques may also work for dividers.
Keywords :
VLSI; dividing circuits; integrated circuit modelling; integrated logic circuits; multiplying circuits; shift registers; table lookup; VLSI systems design; arithmetic logic unit; cycle-accurate RTL level power estimation; dividers; functional units; lookup table; multipliers; partitioning power modeling; power characterization; power consumption; register files; shifters; simulation time reduction; table size reduction; Adders; Circuit simulation; Clustering algorithms; Computer science; Context modeling; Energy consumption; Power dissipation; Power engineering and energy; Statistics; Table lookup;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Signals, Systems, and Computers, 1999. Conference Record of the Thirty-Third Asilomar Conference on
ISSN :
1058-6393
Print_ISBN :
0-7803-5700-0
Type :
conf
DOI :
10.1109/ACSSC.1999.832434
Filename :
832434
Link To Document :
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