Response of 74XX logic circuits to ESD transients

The susceptibility of digital equipment to external transients is of considerable importance in design, both to ensure a reliable instrument, and to ensure that the instrument will meet contractual and legal EMC requirements. A major problem with digital products is susceptibility to single event upset typically caused by an external electrostatic discharge (ESD). Often, the form such an upset takes is an invalid change of state of a latched device, somewhere within the circuit, which corrupts the circuit operation. Most of the EMC design principles that have evolved over the last couple of decades have concentrated on minimizing the interference amplitude that is present at a susceptible circuit node, such as a logic input, by focussing attention on the coupling path to that node. While this is a valid and necessary approach, attention can also be given to minimizing the inherent susceptibility of a given node. This paper reports the results of observations made on the susceptibility to a local ESD event of different samples of a specific device