Study of the variation in electromigration performance from lot to lot variations and the implications for design rule generation

A principle effort during the development of any new semiconductor process is that of insuring the inherent reliability of material made with that process. However, despite its importance it continues to be a largely un-standardized process with great variations across the industry. Designing a qualification process comes with the challenge of optimizing the balance between a realistic prediction of product lifetime and its expected variations, and being reasonable in terms of time and money spent Additional challenges that arise as the technology advances include the need to extrapolate the results from a minimal population of failures under accelerated testing to the reliability for a device with perhaps millions of failure elements. This procedure must consider process variability from wafer-to-wafer and lot-to-lot, and the need for increased reliability with less reliable technologies and inherently less reliable materials. In this study we investigated the efficacy of common qualification practices used in the industry for electromigration reliability assessments by observing the reliability of 29 lots to projections made from arbitrary subsets of 3 to 6 lots as is commonly practiced in industry and considered the impact of uncertainty as a result of lot-to-lot variation on those projections. Since design rules are generally generated from this sort of analysis, we calculated the allowable current density to achieve at most 0.1% failure at 10 years for a chip containing 1,000 failure elements, defined as a conductor carrying the maximum current density at 100% duty cycle. Here we assumed n=1 kinetics and an activation energy of 0.9 eV.