Comparison of duty-cycle effects at room temperature in SiON and HfO2 gate PMOS FETS

The existence of multiple, physically distinct components of Negative Bias Temperature Instability requires a measurement methodology which allows the extraction of each component independently. In this paper we present results obtained at room temperature, which minimizes both the interface state and switching trap components, allowing us to explore the trapping of holes at preexisting defects in the oxide. This is done for both SiON and HfO₂/SiO₂ oxide stacks of similar total thickness. Results are presented for both pseudo-DC and pulse stressing including the dependence of the pulse measurements on duty cycle. A two trap model using the Tewksbury formalism is proposed to predict the results.