BTI and other reliability issues in high mobility channel devices discussion group

• Some use ΔVth=30mV, some 50mV (some anonymously confessed 100mV but on a relaxed technology) • For logic (RO) what matters is ΔIDsat: a generally accepted failure criterion is 10% decrease • It converts into a 10% RO frequency degradation — RO is representative of critical paths in a microprocessor • However the relation between ΔVth and ΔIDsat depends on headroom — issue for low VDD technologies: larger ΔIDsat for given ΔVth • Hence ΔVth criterion might me technology/design specific • For lot-to-lot monitoring a ΔVth criterion is advisable because reflects only oxide/interface quality, while the conversion ΔVth → ΔIDsat depends on transport properties which can be affected by orthogonal process effects • For SRAM a ΔVth failure criterion is more suited. — However different criterion for nMOS and pMOS might be chosen. • Agreed that foundries should supply not only max. operating voltage (for a given failure criterion), but also BTI time-, voltage-, and temperaturedependences • Apparently this is already happening (foundries provide models for TDDB, HCI, BTI) • For this purpose empirical models are preferred w.r.t. physical models because of reduced number of parameters • Designers use such models to optimize their specific designs • It would be advisable to include these models in standard CAD design tools so that they could be applied seamlessly to any circuit design — a concern is the computational power required • However, models are typically calibrated for logic (big cash element), and therefore mixed signal BTI qualification is apparently often performed by the customer on their designed prod- ct