Special interest group I: Product reliability assurance: From wafer technology qualification to chip-package-board interaction

State-of-the-art semiconductor technology capability assessments — including those technologies currently under development — are based still to a great extent on the methodology formulated in the JEDEC foundry process qualification guideline [1] that was published in its first version in 2004. Since, it became a quasi-standard in industry, because it incorporates or references test descriptions, test vehicle / structure requirements as well as failure / assessment criteria for commonly associated failure mechanisms [2] in one compact work description. While a semiconductor product designed in a generic silicon based CMOS logic process is considered as qualified when a qualified semiconductor technology and device library qualification plus device qualification and package qualification [3,4] have been successfully completed, this simple methodology is no longer sufficient and already no longer used for modern semiconductor and assembly integration schemes.