A novel performance-driven placement based on hybrid genetic algorithm

Author

Yoshikawa, Masaya ; Terai, Hidekazu

Author_Institution

Dept. of VLSI Syst. Design, Ritsumeikan Univ., Kyoto, Japan

Volume

3

fYear

2005

fDate

6/27/1905 12:00:00 AM

Firstpage

1203

Abstract

Deep-sub-micron technology (DSM) of 0.18 micron and below enable the integration of logical circuits having more than 10 million gates. In such a DSM technology, layout design has become the most important design phase. This paper discusses a novel performance-driven placement technique. The proposed algorithm based on hybrid genetic algorithms (GA) has a two-level hierarchical structure. For selection control, new objective functions are introduced for improving power consumption, interconnect delay, wire congestion and chip area. Experimental results show improvement comparison with commercial EDA tool.

Keywords

VLSI; genetic algorithms; integrated circuit design; integrated logic circuits; chip area; commercial EDA tool; deep-submicron technology; hybrid genetic algorithm; interconnect delay; layout design; logical circuits integration; objective functions; performance-driven placement technique; power consumption; selection control; two-level hierarchical structure; wire congestion; Delay; Electronic design automation and methodology; Energy consumption; Genetic algorithms; Integrated circuit interconnections; Large scale integration; Transistors; Very large scale integration; Voltage; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Mechatronics and Automation, 2005 IEEE International Conference

Print_ISBN

0-7803-9044-X

Type

conf

DOI

10.1109/ICMA.2005.1626724

Filename

1626724