DocumentCode :
3568602
Title :
CMOS subharmonic downconverter using an LNTA front-end
Author :
Fan Jiang ; Saavedra, Carlos E.
Author_Institution :
Ericsson Canada Inc., Ottawa, ON, Canada
fYear :
2014
Firstpage :
5
Lastpage :
8
Abstract :
To mitigate the higher noise figure (NF) of CMOS-based subharmonic mixers (SHMs) relative to their diode-based counterparts, this paper proposes the use of a low-noise transconductance amplifier (LNTA) ahead of the mixing core. The LNTA has a noise-cancelling topology that enables the mixer to have a high conversion gain and low NF over the RF input band of 4.5 GHz to 8.5 GHz. A chip was fabricated on a standard 130 nm CMOS process to validate the concept and measurement results reveal that the mixer can yield a conversion gain of 14.5±1.5 dB and a double-sideband noise figure of 9.25±1.25 dB over the RF band. The mixer´s IP1dB is -10.8 dBm and its IIP3 is -3.7 dBm while its IIP3 is +6.5 dBm and its OIP3 is +13.8 dBm. The circuit core occupies an area of 0.49 mm2 on the silicon die.
Keywords :
CMOS analogue integrated circuits; MMIC mixers; convertors; low noise amplifiers; CMOS process; CMOS subharmonic downconverter; CMOS-based SHM; CMOS-based subharmonic mixers; LNTA front-end; NF mitigation; RF input; circuit core; diode-based counterparts; double-sideband noise figure; frequency 4.5 GHz to 8.5 GHz; low-noise transconductance amplifier; noise figure mitigation; noise-cancelling topology; silicon die; size 130 nm; CMOS integrated circuits; Gain; Impedance; Mixers; Noise; Noise measurement; Radio frequency;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on
Type :
conf
DOI :
10.1109/ICECS.2014.7049907
Filename :
7049907
Link To Document :
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