Linear regression techniques for efficient analysis of transistor variability

Prior art on time-zero/-dependent variability shows its importance for digital system reliability throughout a typical integrated circuit (IC) lifetime. Timing analysis results could be questionable if the impact of such variations is not taken properly into consideration. Modern models can accurately capture transistor variability but they suffer from prolonged execution times. In this paper, we employ linear regression analysis to accelerate transistor variability estimation. Compared to commercial transistor-level Static Timing Analysis (STA) tools, we achieve a 4.63× average speedup and a 3.56× average memory usage reduction for standard cells and ISCAS85 benchmark circuits, with negligible accuracy degradation.