Compensation of timing mismatches in time-interleaved analog-to-digital converters through transfer characteristics tuning

We analyze transfer characteristic mismatches of sample-and-hold circuits in time-interleaved analog-to-digital converters and show their intrinsic connection to aperture delay mismatches. Both cause linear-phase mismatches, i.e., timing mismatches, which significantly degrade the signal-to-noise ratio. Based on our analysis, we introduce a novel power-saving method to correct timing mismatches among the channels by tuning the transfer characteristics of the sample-and-holds. Simulation results confirm the prospects of the presented method.