Title :
Effects of the NoC architecture in the performance of NoC-based MPSoCs
Author :
Silva, Douglas R. G. ; Oliveira, Bruno S. ; Moraes, Fernando G.
Author_Institution :
Comput. Sci. Dept., PUCRS Univ., Porto Alegre, Brazil
Abstract :
The goal of this work is to evaluate the impact of multiple Network-on-Chip (NoC) architectural parameters over the performance of applications running on Multiprocessors Systems-on-Chip (MPSoCs) using message passing as communication protocol. Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to achieve the full potential of MPSoCs, therefore, the adoption of NoCs is a trend for the communication infrastructure in MPSoCs due to their performance compared to bus-based architectures and scalability compared to crossbar-based architectures. However, there is an important gap in the literature with works evaluating the impact of NoC parameters in the performance of applications running in MPSoCs. This work proposes the evaluation of how different NoC parameters affect applications running in a real MPSoC, trying to answer the following question: how does a given NoC parameter affect the performance of the MPSoC?
Keywords :
message passing; multiprocessing systems; network-on-chip; parallel architectures; performance evaluation; system-on-chip; NoC architecture; NoC-based MPSoC; bus-based architectures; communication infrastructure; communication protocol; crossbar-based architectures; message passing; multiprocessors systems-on-chip; network-on-chip architectural parameters; Clocks; Jitter; Ports (Computers); Random access memory; Routing; Topology; Transform coding; NoC-based MPSoC; NoCs; performance evaluation; routing; topology;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on
DOI :
10.1109/ICECS.2014.7050014
