Title :
Subthreshold passive RF tag´s PIE decoder design with wide tolerance and custom ratioed logic cells
Author :
Weiwei Shi ; Chiu-Sing Choy
Author_Institution :
Shenzhen Key Lab. of Adv. Commun. & Inf. Process., Shenzhen Univ., Shenzhen, China
Abstract :
A subthreshold PIE decoder design with wide tolerance for passive RF devices is presented. For the consideration of low power and low-voltage supply, energy-aware structure with mixed counter and pre-counted addition are proposed. They also greatly reduces the impact of frequency variation. An innovative logic style is also proposed to achieve faster logic propagation in critical paths. It is an optimization from previous ratioed logics with pull-up current control and modified branches tailored to very-low supply voltage. The subthreshold active power can be suppressed to a comparable magnitude of static CMOS leakage. Fabricated in 90nm CMOS technology, the proposed PIE decoder can operate at 0.26-0.8 V with working clock frequency of equivalently 1.28-4.1 MHz, enhancing the overall robustness of the RF transponders.
Keywords :
CMOS logic circuits; UHF integrated circuits; circuit optimisation; counting circuits; decoding; logic design; low-power electronics; power aware computing; radiofrequency identification; transponders; CMOS technology; PIE decoder design; RF transponders; custom ratioed logic cells; energy-aware structure; frequency 1.28 MHz to 4.1 MHz; frequency variation impact reduction; logic propagation; low power electronics; low-voltage supply; mixed counter; optimization; pre-counted addition; pull-up current control; pulse interval encoding decoder; size 90 nm; static CMOS leakage; subthreshold active power suppression; subthreshold passive RF tag; voltage 0.26 V to 0.8 V; Baseband; CMOS integrated circuits; Clocks; Decoding; Delays; Radiation detectors; Radio frequency;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on
DOI :
10.1109/ICECS.2014.7050018
