Area reduction on interconnect optimized floorplan using deadspace utilization

Interconnect optimization has become the major concern in floorplanning. Many approaches would use simulated annealing (SA) with a cost function composed of a weighted sum of area, wirelength and interconnect cost. These approaches can reduce the interconnect cost efficiently but the area penalty of the interconnect optimized floorplan is usually quite large. In this paper, we propose a new approach called deadspace utilization (DSU) to reclaim the unused area of an interconnect optimized floorplan by linear programming. Since modules are not necessarily rectangular in shape in floorplanning, some deadspace can be redistributed to the modules to increase the area occupied by the modules. If the area of each module can be expanded by the same ratio, the whole floorplan can be compacted by that ratio to give a smaller floorplan. In addition, we can limit the compaction ratio to prevent over-congestion. Experiments show that we can apply this deadspace utilization technique to reduce the area and wirelength of an interconnect optimized floorplan further while the constraint on routability and congestion can be maintained at the same time.