Analytical ramp delay model for distributed on-chip RLC interconnects

In the past, gate delay was the dominant factor in determining circuit performance. However, as feature size becomes smaller and chip area becomes larger in integrated circuits, interconnect delay has become an increasingly important factor in determining circuit performance. In this paper, we present an analytical delay calculation approach for a distributed RLC interconnect line that maintains the effectiveness and the efficiency of past RC interconnect models, but significantly improving their accuracy for deep submicron (DSM) designs.