Title :
Closed-loop simulation method for evaluation of static offset in discrete-time comparators
Author :
Gines, A.J. ; Peralias, E. ; Leger, G. ; Rueda, A.
Author_Institution :
Inst. de Microelectron. de Sevilla (IMSE), Univ. de Sevilla, Sevilla, Spain
Abstract :
This paper presents a simulation-based method for evaluating the static offset in discrete-time comparators. The proposed procedure is based on a closed-loop algorithm which forces the input signal of the comparator to quickly converge to its effective threshold. From this value, the final offset is computed by subtracting the ideal reference. The proposal was validated using realistic behavioral models and transistor-level simulations in a 0.18μm CMOS technology. The application of the method reduces by several orders of magnitude the number of cycles needed to characterize the offset during design, drastically improving productivity.
Keywords :
CMOS analogue integrated circuits; comparators (circuits); discrete time systems; integrated circuit modelling; CMOS technology; closed-loop algorithm; closed-loop simulation method; discrete-time comparators; realistic behavioral models; size 0.18 mum; static offset evaluation; transistor-level simulations; Accuracy; Clocks; Computational modeling; Convergence; Estimation; Semiconductor device modeling; Transient analysis; Flash-ADC; comparator offset evaluation; discrete-time; simulation-based techniques;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on
DOI :
10.1109/ICECS.2014.7050041
