DocumentCode
3569035
Title
Low power bank-based multi-port SRAM design due to bank standby mode
Author
Zhu, Zhaomin ; Johguchi, Koh ; Mattausch, Hans J?¼rgen ; Koide, Tetsushi ; Hironaka, Tetsuo
Author_Institution
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
Volume
1
fYear
2004
Abstract
A low power multi-port SRAM design method based on banks switchable between active and standby mode is described. Speed decrease is prevented by use of an access method with hidden precharge-time. More than 56% power reduction can be achieved when 64 banks are used to implement a 4-port SRAM. A 4 kB SRAM with 4 ports and 16 banks has been designed and fabricated for verification.
Keywords
SRAM chips; integrated circuit design; low-power electronics; multiport networks; 4 kB; bank active mode; bank standby mode; hidden precharge time; low power bank based SRAM design; multiport SRAM design; power reduction; Artificial intelligence; Capacity planning; Circuits; Data processing; Decoding; Design methodology; Memory architecture; Multimedia systems; Random access memory; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN
0-7803-8346-X
Type
conf
DOI
10.1109/MWSCAS.2004.1354054
Filename
1354054
Link To Document