Automatic layout generation of power MOSFET transistors in bulk CMOS

This paper presents an automatic layout generation tool for power MOSFET transistors in bulk CMOS. It is implemented in an open multiplatform language, Python, and is capable of generating area and power optimized transistors, which automatically meet DRC, DFM and ESD rule sets. The tool is able to fast create technology independent layouts, easily ported between technology nodes, and directly export designs into GDSII format, allowing complete independence from any IC design platform. The tool is demonstrated in a design of a half-bridge power stage for a Class-D amplifier and compared with a reference manual design - the results obtained are superior: lower resistance and dynamic power losses, while keeping almost the same overall area but speeding-up the design flow by several orders of magnitude.