Radiation-tolerant standard cell synthesis using double-rail redundant approach

In this paper, we describe a new logic family based on a Double-Rail Redundant Approach, that we call D2RA. Each cell receives both the input bits and their negated values, and is made of two main blocks: the first one produces the output bit, the second one the inverted output bit. When a bit and its negated value have the same logic value, then an error occurred. In such a case, the two output bits are set to the same value. This approach allows to avoid single event effects in presence of radiation. The synthesis of the logic function performed by each cell is based on an algorithm that minimizes the number of transistors in a fully-CMOS design approach. We demonstrate that the proposed approach is correct for any number of input variables, and gives the minimum form with respect to the constraints of the logic model.