Configurable and high-throughput architectures for Quasi-cyclic low-density parity-check codes

LDPC codes are currently the most promising coding technique to achieve the Shannon capacity, making them very popular in modern telecommuncation applications. Despite the attractivity stemming from their effectiveness, encoding and decoding LDPC codes is a rather complex task, due to the size and structure of the codes, especially when considering the ever increasing need for higher throughput in communication networks. All these constraints are setting the demand for new encoding/decoding architectures very high. In this paper, we propose effective encoder and decoder architectures for the Quasi-Cycle subclass of LDPC codes. The main features being targeted are pre-synthesis configurability and high throughput. QC-LDPC codes exhibit a highly regular structure in their parity check matrices making easier the design process to obtain the high levels of architectural parallelism necessary to achieve the required high throughputs. In order to validate our design, several encoder and decoder were implemented on FPGAs of the Altera Stratix III and Xilinx Virtex4 using different code parameters (block length and code rate) for QC-LPDC codes from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.1 In) protocols. Throughputs up to 32 Gbits/s and 732 Mbits/s have been achieved for the encoder and decoder, respectively.