Holistic technology optimization and key enablers for 7nm mobile SoC

We systematically investigated the impact of R and C scaling to 7nm node (N7) by accounting for FEOL and BEOL holistically. Speed-power performance of plainly scaled N7 turns out to be degraded compared to previous node. BEOL wire resistance (R_wire) multiplied by logic gate input pin cap (C_pin), R_wire×C_pin, is identified as a major limiter of performance and power at N7. Reducing C_pin is crucial to mitigate abruptly rising BEOL R_wire effect. Depopulation of fin is one of most effective methods to reduce C_pin, and scale the logic gate area. Air Spacer (AS) on transistor sidewall is proposed to further reduce C_pin, whose benefit is enhanced by reduction of other C_pin components. Careful choice of routing metal stack ameliorates adverse effect of R_wire. Wrap-Around-Contact (WAC) over Source and Drain of scaled fin pitch (P_fin) is needed to reduce transistor resistance (R_tr). Fin depopulation with other cost effective process innovations significantly improve Power-Performance-Area-Cost (PPAC) of N7, enabling continued scaling of mobile System on a Chip.