Active-lite interposer for 2.5 & 3D integration

Author

Hellings, G. ; Scholz, M. ; Detalle, M. ; Velenis, D. ; de Potter de ten Broeck, M. ; Roda Neve, C. ; Li, Y. ; Van Huylenbroek, S. ; Chen, S.-H. ; Marinissen, E.-J. ; La Manna, A. ; Van der Plas, G. ; Linten, D. ; Beyne, E. ; Thean, A.

Author_Institution

imec, Leuven, Belgium

fYear

2015

Abstract

Adding functionality to a passive Si interposer used in 2.5/3D integration, can result in system cost reductions. In this work, active components (diodes, BJT, ...) have been integrated on Si interposer using a new low-mask process flow. This low-cost process enables: (1) to move part of the area hungry ESD protection from the stacked dies to the interposer; (2) the realization of pre-bond testable interposers (DFT); and (3) components for analog circuits (diodes, npn, SCR, resistor).

Keywords

analogue integrated circuits; design for testability; electrostatic discharge; elemental semiconductors; integrated circuit testing; silicon; three-dimensional integrated circuits; 2.5D integration; 3D integration; DFT; ESD protection; Si; active-lite interposer; analog circuits; design for testability; low-mask process flow; passive interposer; prebond testable interposers; system cost reductions; Clamps; Electrostatic discharges; Field programmable gate arrays; FinFETs; Implants; Silicon; Testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI Technology), 2015 Symposium on

ISSN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2015.7223647

Filename

7223647