• DocumentCode
    3569443
  • Title

    High voltage I/O FinFET device optimization for 16nm system-on-a-chip (SoC) technology

  • Author

    Miyashita, T. ; Kwong, K.C. ; Wu, P.H. ; Hsu, B.C. ; Chen, P.N. ; Tsai, C.H. ; Chiang, M.C. ; Lin, C.Y. ; Wu, S.Y.

  • Author_Institution
    Taiwan Semicond. Manuf. Co. Ltd., Hsinchu, Taiwan
  • fYear
    2015
  • Abstract
    High voltage I/O FinFET device optimization for a 16nm system-on-a-chip (SoC) technology is presented. After careful optimization through high electric field (E-field) mitigation by junction engineering, I/O FinFET devices with leakage current reduction by 1~2 orders, hot carrier injection (HCI) lifetime improvement by 2.8×/1.2× for N- and PMOS, respectively, and junction breakdown voltage (Vbd) improvement by more than 0.8V are achieved.
  • Keywords
    MOSFET; hot carriers; leakage currents; optimisation; system-on-chip; high voltage FinFET device optimization; hot carrier injection; junction breakdown voltage; leakage current reduction; system-on-a-chip technology; FinFETs; Floors; Human computer interaction; Junctions; Leakage currents; Temperature dependence;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Technology (VLSI Technology), 2015 Symposium on
  • ISSN
    0743-1562
  • Type

    conf

  • DOI
    10.1109/VLSIT.2015.7223658
  • Filename
    7223658
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3569443