Title :
A novel ALD SiBCN low-k spacer for parasitic capacitance reduction in FinFETs
Author :
Yamashita, T. ; Mehta, S. ; Basker, V.S. ; Southwick, R. ; Kumar, A. ; Kambhampati, R. ; Sathiyanarayanan, R. ; Johnson, J. ; Hook, T. ; Cohen, S. ; Li, J. ; Madan, A. ; Zhu, Z. ; Tai, L. ; Yao, Y. ; Chinthamanipeta, P. ; Hopstaken, M. ; Liu, Z. ; Lu, D.
Author_Institution :
IBM Res., Albany, NY, USA
Abstract :
FinFET has become the mainstream logic device architecture in recent technology nodes due to its superior electrostatic and leakage control [1,2,3,4]. However, parasitic capacitance has been a key performance detractor in 3D FinFETs. In this work, a novel low temperature ALD-based SiBCN material has been identified, with an optimized spacer RIE process developed to preserve the low-k value and provide compatibility with the down-stream processes. The material has been integrated into a manufacturable 14nm replacement-metal-gate (RMG) FinFET baseline with a demonstrated ~8% performance improvement in the RO delay with reliability meeting the technology requirement [4]. A guideline for spacer design consideration for 10nm node and beyond is also provided based on the comprehensive material properties and reliability evaluations.
Keywords :
MOSFET; boron compounds; capacitance; carbon compounds; low-k dielectric thin films; semiconductor device reliability; silicon compounds; sputter etching; 3D FinFET; RMG FinFET baseline; RO delay; SiBCN; comprehensive material properties; down-stream processes; mainstream logic device architecture; novel low temperature ALD-based SiBCN material; optimized spacer RIE process; parasitic capacitance; reliability evaluations; replacement-metal-gate FinFET baseline; spacer design consideration; Delays; Films; FinFETs; Leakage currents; Reliability; Silicon compounds; Very large scale integration;
Conference_Titel :
VLSI Technology (VLSI Technology), 2015 Symposium on
DOI :
10.1109/VLSIT.2015.7223659
