DocumentCode
3569533
Title
Loop list scheduler for DSP algorithms under resource constraints
Author
Parhi, Keshab
fYear
1993
Firstpage
1662
Lastpage
1665
Keywords
Control system synthesis; Delay; Digital signal processing; Iterative algorithms; Mars; Optimal scheduling; Pipeline processing; Scheduling algorithm; Signal processing algorithms; Signal synthesis;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Print_ISBN
0-7803-1281-3
Type
conf
Filename
692985
Link To Document