Title :
Design and demonstration of reliability-aware Ge gate stacks with 0.5 nm EOT
Author :
Lu, C. ; Lee, C.H. ; Nishimura, T. ; Toriumi, A.
Author_Institution :
Dept. of Mater. Eng., Univ. of Tokyo, Tokyo, Japan
Abstract :
This paper reports a novel material/process-based design for reliability-aware Ge gate stack for the first time. Initially good characteristics of Ge gate stacks do not necessarily guarantee the long-term device reliability. To overcome the big hurdle, we have investigated the stability of GeO2 network as well as the formation of new high-k. The very robust Ge gate stack with both 0.5 nm EOT and sufficiently low Dit is demonstrated.
Keywords :
elemental semiconductors; germanium; germanium compounds; semiconductor device reliability; EOT; Ge; GeO2; device reliability; equivalent oxide thickness; reliability-aware germanium stack; size 0.5 nm; Hafnium compounds; High K dielectric materials; Logic gates; Robustness; Stress; Thermal stability;
Conference_Titel :
VLSI Technology (VLSI Technology), 2015 Symposium on
DOI :
10.1109/VLSIT.2015.7223686
