A comparison of arsenic and phosphorus extension by Room Temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions

Author

Sasaki, Y. ; Ritzenthaler, R. ; De Keersgieter, A. ; Chiarella, T. ; Kubicek, S. ; Rosseel, E. ; Waite, A. ; del Agua Borniquel, J. ; Colombeau, B. ; Chew, S.A. ; Kim, M.S. ; Schram, T. ; Demuynck, S. ; Vandervorst, W. ; Horiguchi, N. ; Mocuta, D. ; Mocut

Author_Institution

imec, Leuven, Belgium

fYear

2015

Abstract

We compare As and P extension implants for NMOS Si bulk FinFETs with 5nm wide fins. P implanted FinFETs shows improved I_ON, +15% with Room Temperature (RT) ion implantation (I/I) and +9% with hot I/I, keeping matched Short Channel Effects (SCE) for gate length (L_G) of 30nm compared with As implanted FinFETs. Based on TCAD work, P increases activated dopant concentration in extension compared with As and 5nm fin suppresses off state leakage current under the gate efficiently even in P extension case though P diffusion is faster than As.

Keywords

MOSFET; arsenic; elemental semiconductors; ion implantation; leakage currents; nanotechnology; phosphorus; semiconductor device models; silicon; technology CAD (electronics); As; NMOS bulk-FinFET; P; Si; TCAD; hot ion implantation; leakage current; room temperature; short channel effects; size 30 nm; size 5 nm; size 7 nm; temperature 293 K to 298 K; FinFETs; Implants; Leakage currents; Logic gates; Performance evaluation; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI Technology), 2015 Symposium on

ISSN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2015.7223691

Filename

7223691