Title :
WSI design of a radix 2 butterfly using macrocell pools
Author :
Callaway, Thomas K. ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. At the circuit level, the strategy used is macrocell pooled redundancy. There are two basic types of macrocell pooled redundancy: 1 from N, and M from N. These two strategies are applied to the design of a radix 2 butterfly circuit for an FFT processor, and the effects of the choice of pooling strategy upon the yield are shown
Keywords :
VLSI; cellular arrays; fast Fourier transforms; hypercube networks; microprocessor chips; redundancy; FFT processor; WSI design; circuit level; design strategy; fault circumvention strategy; macrocell pools; pooled redundancy; pooling strategy; radix 2 butterfly; yield; Aircraft; Circuit faults; Equations; Fault tolerance; Integrated circuit interconnections; Macrocell networks; Random access memory; Read-write memory; Redundancy; Statistical distributions;
Conference_Titel :
Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
Print_ISBN :
0-7803-1850-1
DOI :
10.1109/ICWSI.1994.291239
