Physical level design and analysis of fast fourier transforms using Vedic Mathematics

Author

Srinivasan, Sitaramiah Venkataramana ; Razak, Abdul

Author_Institution

Microelectron., Birla Inst. of Technol. & Sci., Dubai, United Arab Emirates

fYear

2014

Firstpage

1

Lastpage

4

Abstract

The objective of the paper is to design and analyze a physical level chip for Fast Fourier Transform using the concepts from Vedic Mathematics with VLSI 90nm technology. Vedic Mathematics in certain fields are faster than regular mathematical computations. Implementing the idea of Vedic mathematics in designing a Fast Fourier Transform chip will improve the efficiency of calculation and will produce a less time consumption. Fast Fourier Transforms is a very important concept in various digital signal processing applications and thus timing will play a key role. The algorithm for Vedic Mathematics is developed by means of Hardware description Language (HDL) code and analyzed using design compiler tool from Synopsys, Inc.

Keywords

VLSI; fast Fourier transforms; hardware description languages; integrated circuit design; HDL code; Synopsys Inc; VLSI; Vedic mathematics; design compiler; digital signal processing application; fast Fourier transforms analysis; hardware description language; physical level design; size 90 nm; Algorithm design and analysis; Complexity theory; Fast Fourier transforms; Hardware design languages; Logic gates; Transistors; VLSI; binary sequences; computational efficiency; mathematics; nanotechnology;

fLanguage

English

Publisher

ieee

Conference_Titel

Fundamentals of Electrical Engineering (ISFEE), 2014 International Symposium on

Print_ISBN

978-1-4799-6820-6

Type

conf

DOI

10.1109/ISFEE.2014.7050566

Filename

7050566