Improved speed clock swing-reduced variable sampling window flip-flop

This paper presents a speed enhancement of the recently proposed high performance clock swing-reduced variable sampling window flip-flop. Based on a restructuring the proposed flip-flop to reduce the number of series transistors in the discharging path in order to maintain the lowest time constant, the discharging speed of the original clock swing-reduced variable sampling window flip-flop is improved by one third without sacrificing other system characteristics such as power consumption and area overhead. The idea is demonstrated on a 0.25 μm CMOS process.