Title :
A reliable and high voltage compatible CMOS I/O buffer
Author :
Chow, Hwang-Cherng ; Chen, You-Gang
Author_Institution :
Graduate Inst. of Electron. Eng., Chang Gung Univ., Taoyuan, Taiwan
Abstract :
A high voltage tolerant and reliable CMOS I/O buffer without using thick-oxide devices is presented. By the floating n-well technique, the proposed design has a simpler structure and the good gate-oxide reliability is achieved. In addition, it is dc leakage free and has no redundant pad for dual powers. From the simulation results, the proposed circuit can demonstrate both speed enhancement about 20% in pull-up operation and 50% saving in area. Therefore, the proposed I/O buffer is very suitable for mixed voltage interface applications.
Keywords :
CMOS integrated circuits; buffer circuits; circuit simulation; integrated circuit design; integrated circuit reliability; power integrated circuits; circuit simulation; floating n-well technique; gate oxide reliability; high voltage compatible CMOS I/O buffer; integrated circuit design; mixed voltage interface applications; speed enhancement; Art; Circuit simulation; Costs; Energy consumption; Integrated circuit technology; Low voltage; MOS devices; Power supplies; Reliability engineering; Threshold voltage;
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
DOI :
10.1109/MWSCAS.2004.1354392
