DocumentCode :
3570054
Title :
A class of zero wasted area floorplan for VLSI design
Author :
Kai Wang
Author_Institution :
University of Illinois
fYear :
1993
Firstpage :
1762
Lastpage :
1765
Keywords :
Circuits; Conductors; Graph theory; Iterative algorithms; Partitioning algorithms; Power dissipation; Resistors; Routing; Very large scale integration; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Print_ISBN :
0-7803-1281-3
Type :
conf
Filename :
693010
Link To Document :
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