Title :
NoC Based Multiplier-Less Constant Geometry FFT Architecture
Author :
Prasad, N. ; Chakrabarti, Indrajit ; Chattopadhyay, Santanu
Author_Institution :
Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, Kharagpur, India
Abstract :
This paper reports the architecture of a Network-on-Chip (NoC) based constant geometry FFT (CGFFT). The twiddle factor complex multiplications have been realized using new distributed arithmetic (NEDA) blocks. The architecture, which contains four processing elements (PEs) that are mapped by considering the data flow between the stages of FFT, has been mapped on to a 2 × 2 mesh NoC. The known traffic pattern and known data source-destination locations have reduced the latency of the router by minimizing the buffer size. The architecture has been implemented using Xilinx Kintex7 FPGA and has been simulated using a cycle-accurate SystemC based simulator.
Keywords :
data flow computing; distributed arithmetic; fast Fourier transforms; field programmable gate arrays; network-on-chip; CGFFT; NEDA blocks; NoC; Xilinx Kintex 7 FPGA; cycle-accurate SystemC based simulator; data flow; data source-destination locations; multiplier-less constant geometry FFT architecture; network-on-chip; new distributed arithmetic; processing elements; traffic pattern; twiddle factor complex multiplications; Algorithm design and analysis; Clocks; Computer architecture; Field programmable gate arrays; Geometry; Nickel; Program processors; CGFFT; FPGA; NEDA; NoC; Xilinx;
Conference_Titel :
Emerging Applications of Information Technology (EAIT), 2014 Fourth International Conference of
DOI :
10.1109/EAIT.2014.45
